Code 300 32 Sdr Sdram

Pierre schrieb: > Hello > > I use a Virtex-II Pro with PowerPC at 300 MHz, 8 kB IOCM, 32 kB DOCM and > external 32 MB SDRAM (connected on PLB ) > > When I read 10 times 32 MB on my SDRAM, that takes 3.7' and when I write > the 320MB on the SDRAM it takes 9.6' without burst support and 6' with > burst support. > > Did someone knows why the read rate is 85 MByte/s and 53 MB/s(maximum ) for > writing?

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For one thing, the PLB runs at 100MHz maximum frequency, even if the processor runs much faster. So that's one limitation, only a third of the maximum rate.

Another is the data bandwidth on your SDRAM: is it really 64 bit or only 32bit? On most eval boards it's 16 oder 32bit, so that's another factor of 2 or 4 less (if it's SDR-DRAM). Then you have to think about refresh and all that. Even if you do bursts, the controller has to refresh the memory regularly, so that takes away even more performance. Then you have to consider that the PLB is a bus structure. So even if there's only one component on the bus, there's always a few clock cycles for bus arbitration when you start a transfer. Then it depends on your program.

For example, if you use a for-loop to write to and read from every address one after another, then what you actually do is single 32bit-accesses, meaning that for each 32bit-data-word you read there's bus arbitration, DRAM latency, maybe you have to wait a few clock cycles because the DRAM is currently refreshing and so on. This added up maybe gives you as much as 8 clock cycles (at 100MHz) to read a mere 4 bytes, multiplied by 3 gives you 24 CPU clock cycles (at 300MHz) for one single access, if all goes really bad, and there you have your ~50MB/s, assuming your RAM is a 32 bits wide SDR-DRAM. I don't know how bursts are handled in the DDR-core for the PLB, so I can't comment on that.

But in DDR-SDRAM burst can only be as longs a 8 ticks, then the whole SDRAM-latency-thing starts again. Neither can I give any useful guesses as to why writing should be slower than reading, could be some issues with caching. In cases like this it could also be useful to debug the generated ELF-file to see how your code maps to assembly instructions. On Thu, 30 Jun 2005 15:11:17 +0200, Sean Durkin wrote: >Pierre schrieb: >> Hello >> >> I use a Virtex-II Pro with PowerPC at 300 MHz, 8 kB IOCM, 32 kB DOCM and >> external 32 MB SDRAM (connected on PLB ) >> >> When I read 10 times 32 MB on my SDRAM, that takes 3.7' and when I write >> the 320MB on the SDRAM it takes 9.6' without burst support and 6' with >> burst support. >> >> Did someone knows why the read rate is 85 MByte/s and 53 MB/s(maximum ) for >> writing? I have no knowledge of this implementation, but common sense should tell you that reads are inherently slower than writes when both are optimally implemented. For a write, you can throw the address & data at the RAM at the same time, and let the RAM and controller get on with it while you go do something else (other than reading from the same RAM).